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| OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER SYMBOL 74OL6000 74OL6001 74OL6010 74OL6011 LSTTL TO PACKAGE 6 1 6 BUFFER 1 INVERTER 6 1 DESCRIPTION OPTOLOGICTM is the first family of truly logic compatible optically coupled logic interface gates. The family consists of four device types offering LSTTL to TTL and LSTTL to CMOS interfacing. Each of these interfacing functions is available as a buffer (A=B), or as an inverter (A=B). The LSTTL input compatibility is provided by an input integrated circuit, with industry standard logic levels. This input amplifier IC switches a temperature compensated current source driving a high speed 850 nm AlGaAs LED emitter. This novel integration scheme eliminates CTR degradation over time and temperature. The emitter is optically coupled to an integrated photodetector/high-gain, high-speed output amplifier IC. The superior 15kV/S common-mode noise rejection is ensured through the use of an optically transparent noise shield. The TTL compatible output has a totem-pole with a fan-out of 10. The CMOS compatible output has an open collector Schottkyclamped transistor that interfaces to any CMOS logic between 4.5 and 15 volts. The 74OL6010/11 may also by used to drive power MOSFETS or transistors up to 15 volts. The Optologic coupler family typically offers propagation of delays of 60 ns and can support 15 MBaud data communication. The two input chips and the output chip are assembled in a 6-pin DIP high insulation voltage plastic package. Fairchild's proprietary OPTOPLANAR(R) construction provides a withstand test voltage of 5300 VRMS (1 minute). FEATURES * Industry first LSTTL to TTL and LSTTL to CMOS complete logic-to-logic optocoupler * Incorporates LED drive circuitry -- use as logic gate * Very high speed * Choice of buffer or inverter * Choice of TTL or CMOS compatible output up to 15 volts * Fan-out of 10 TTL loads, fan-in 1 LSTTL load * Internal noise shield -- very high CMR of 15 kV/S * UL recognized (File #E90700) * Same noise immunity as LSTTL/TTL. APPLICATIONS * * * * * * * * Transmission line interface -- receiver and driver Excellent as bridged receiver in fast LAN highways Bus interface Logic family interface with ground loop noise elimination High speed AC/DC voltage sensing Driver for power semiconductor devices Level shifting Replaces fast pulse transformers (c) 2003 Fairchild Semiconductor Corporation Page 1 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER Vcc 22 k TYP. 150 TYP. RL INPUT OUTPUT Vcc LSTTL TO Vcc 74OL6000 74OL6001 74OL6010 74OL6011 GND LSTTL INPUT CIRCUIT OUTPUT GND CMOS OUTPUT CIRCUIT GND TTL OUTPUT CIRCUIT All Inputs 74OL6000/01 Output 74OL6010/11 Output PIN CONFIGURATION 1-VCCI (Input VCC) 2-VIN (Data In) 6-VCCO (Output VCC) 5-VO (Data Out) 3-GND, (Input GND) 4-GNDO (Output GND) DEVICE CONFIGURATION Logic Compatibility Part Number Input 74OL 6000 74OL 6001 74OL 6010 74OL 6011 LSTTL LSTTL LSTTL LSTTL Output TTL TTL CMOS CMOS BUFFER INVERTER BUFFER INVERTER TOTEM POLE TOTEM POLE OPEN COLLECTOR OPEN COLLECTOR Logic Function Output Configuration (c) 2003 Fairchild Semiconductor Corporation Page 2 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER 74OL6000 74OL6001 74OL6010 74OL6011 LSTTL TO SCHEMATIC 74OL OL6000 NOISE SHIELD 74OL OL6001 NOISE SHIELD 74OL OL6010 NOISE SHIELD 74OL OL6011 NOISE SHIELD 1 6 1 6 1 6 1 6 2 5 2 5 2 5 2 5 3 4 3 4 3 4 3 4 LSTLL to TTL Buffer LSTLL to TTL Inverter LSTLL to CMOS Buffer LSTLL to CMOS Inverter (c) 2003 Fairchild Semiconductor Corporation Page 3 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER 74OL6000 74OL6001 74OL6010 74OL6011 LSTTL TO ELECTRICAL CHARACTERISTICS (TA = 0C to 70C Unless otherwise specified) Test Conditions Parameter TTL OUTPUT 74OL6000/01 Input Supply Voltage Output Supply Voltage High-Level Input Voltage Low-Level Input Voltage Input Clamp Voltage High-Level Input Current Low-Level Input Current Input Supply Current (high) Input Supply Current (low) High-Level Output Voltage Symbol Min Typ* Max Units 74OL6000 VCCI VCCO VIH VIL VIK IIH IIL ICCIH ICCIL VOH 4.5 4.5 2.0 5.0 5.0 5.5 5.5 V V V V V A A mA mA V 0.6 Low-Level Output Voltage VOL 0.3 0.5 High-Level Output Current Low-Level Output Current Short-Circuit Output Current Output Supply Current (high) Output Supply Current (low) IOH IOL IOS ICCOH ICCOL 16.0 -5.0 -25.0 9.0 8.0 -40.0 15.0 12.0 -8.0 -10.0 mA mA mA mA mA VIN = VIH VIN = 0.8 V VIN = VIH VIN = VIH VIN = VIL V VIN = 0.8V VIN = 2.0 V 74OL6001 74OL6000/01 1 1 1 1 1 1 1 1 1 1 Notes 0.8 -1.2 1.0 40.0 -200.0 -400.0 10.0 14.0 10.0 14.0 2.4 3.0 VCCI = 4.5 V, II = -18 mA VCCI = 5.5 V, VIH = 4.5 V VCCI = 5.5 V, VIL = 0.4 V VCCI = 5.5 V, VIN = VIH VCCI = 5.5 V, VIN = VIL VCCI = 4.5 V, VCCO = 4.5 V, VIN = 0.8 V IOH = -400 mA VCCI = 4.5 V, VCCO = 4.5 V, IOL = 16 mA VIN = 2.0V VCCI = 4.5 V, VCCO = 4.5 V, IOL = 4 mA VCCI = 4.5 V, VCCO = 4.5 V, VIN = VIL VOH = 2.4 V VCCI = 4.5 V, VCCO = 4.5 V, VIN = 2.0V VOL = 0.6 V VIN = VIL VCCI = 5.5 V, VCCO = 5.5 V, VCCI = 5.5 V, VO = VOH, VIN = VIL VCCO= 5.5 V VCCI = 5.5 V, VO = VOL, VIN = VIH VCCO = 5.5 V 1 1 1 1 1 1 *All typical values are at TA=25C SWITCHING CHARACTERISTCS (TA = 25C Unless otherwise specified) Parameter TTL OUTPUT 74OL6000/01 Propagation Delay Time For Output Low Level Propagation Delay Time For Output High Level Output Rise Time For Output High Level Output Fall Time For Output Low Level Symbol Min tPHL tPLH tr tf Typ 60 70 45 5 Max Units 100 100 ns ns n ns Test Conditions Fig. 15, 17 15, 17 15, 17 15, 17 Notes 1 1 1 1 VCCI = 5 V, VCCO = 5 V (c) 2003 Fairchild Semiconductor Corporation Page 4 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER 74OL6000 74OL6001 74OL6010 74OL6011 LSTTL TO ELECTRICAL CHARACTERISTICS (TA = 0C to 70C Unless otherwise specified) Test Conditions Parameter CMOS OUTPUT 74OL6010/11 Input Supply Voltage Output Supply Voltage High-Level Input Voltage Low-Level Input Voltage Input Clamp Voltage High-Level Input Current Low-Level Input Current Input Supply Current (high) Input Supply Current (low) Low-Level Output Voltage Symbol Min Typ* Max Units 74OL6010 74OL6011 VCCI VCCO VIH VIL VIK IIH IIL ICCIH ICCIL VOL 4.5 4.5 2.0 V V V 0.8 V -1.2 V 1.0 40.0 A -200.0 -400.0 A 10.0 14.0 mA 10.0 14.0 mA 0.6 0.4 0.5 High-Level Output Current Low-Level Output Current IOH IOL 16.0 9.0 Output Supply Current (high) ICCOH 11.0 8.0 Output Supply Current (low) ICCOL 11.0 *All typical values are at TA=25C 18.0 18.0 12.0 mA VIN = VIL VIN = VIH 12.0 mA VIN = VIH VIN = VIL 1.0 100.0 A mA VIN = VIH VIN = VIL V VIN = 0.8V VIN = 2.0V 5.0 5.5 15.0 74OL6010/11 1 1,3 1 1 1 1 1 1 1 1 Notes VIN = 0.8 V VIN = 2.0V VCCI = 4.5 V, II = -18 mA VCCI = 5.5 V, VIH = 4.5 V VCCI = 5.5 V, VIL = -0.4 V VCCI = 5.5 V, VIN = VIH VCCI = 5.5 V, VIN = VIL VCCI = 4.5 V, VCCO = 4.5 V, IOL = 16 mA VCCI = 4.5 V, VCCO = 4.5 V, IOL = 4 mA VCCI = 4.5 V, VOH = 15 V, VCCO = 4.5 - 15 V VCCI = 4.5 V, VOL = 0.6V, VCCO = 4.5 - 15 V VCCI = 5.5 V, VO = VOH, VCCO = 4.5 V VCCI = 5.5 V, VO = VOL, VCCO = 15 V VCCI = 5.5 V, VO = VOL, VCCO = 4.5 V VCCI = 5.5 V, VO = VOL, VCCO = 15 V 1 1 1 1 SWITCHING CHARACTERISTCS (TA = 25C Unless otherwise specified) Parameter TTL OUTPUT 74OL6010/11 Propagation Delay Time For Output Low Level Propagation Delay Time For Output High Level Output Rise Time For Output High Level Output Fail Time For Output Low Level Symbol Min tPHL tPLH tr tf Typ Max Units 60 100 50 5 120 180 ns ns ns ns Test Conditions Fig. 15, 18 15, 18 15, 18 15, 18 Notes 1 1 1 1 VCCI = 5 V, VCCO = 5 V, RL = 470 (c) 2003 Fairchild Semiconductor Corporation Page 5 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER 74OL6000 74OL6001 74OL6010 74OL6011 LSTTL TO ABSOLUTE MAXIMUM RATINGS (TA = 25C unless otherwise specified) Parameter TOTAL DEVICE Storage Temperature Operating Temperature Lead Solder Temperature Power Dissipation EMITTER Input Supply Voltage Input Voltage DETECTOR Average Output Current Output Supply Voltage Output Voltage IO (avg) VCCO VO All 74OL6000/01 74OL6010/11 74OL6000/01 74OL6010/11 40 7 18 7 18 mA V V VCCI VIN All All 7 7 V V TSTG TOPR TSOL PD All All All All -55 to +125 0 to +70 260 for 10 sec 350 C C C mW Symbol Device Value Units ELECTRICAL CHARACERISTICS (TA = 0C to 70C Unless otherwise specified) Parameter 74OL6000/01/10/11 Common Mode Transient Immunity at Logic High Level Output Common Mode Transient Immunity at Logic Low Level Output Common Mode Coupling Capacitance Capacitance (input-output) Withstand Insulation Test Voltage Insulation Resistance CMH CML CCM CI-O VISO RISO 5300 10 5000 15000 V/S V/S pF pF VRMS VI-O = 0, f = 1 MHz TA = 25C, t = 1 min, II-O 1mA VI-O = 500 VDC 2 2 2 VCCI = 5 V, VCCO = 5 V, VCM = 50 Vp-p 16, 19 16, 19 Symbol Min Typ Max Units Test Conditions Fig. Notes -5000 -15000 0.005 0.7 (c) 2003 Fairchild Semiconductor Corporation Page 6 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER 74OL6000 74OL6001 74OL6010 74OL6011 LSTTL TO Figure 1. Input Current vs. Ambient Temperature 100 Figure 2. Input Supply Current vs. Ambient Temperature 15 14 ICCI - INPUT SUPPLY CURRENT (mA) 13 12 11 10 9 8 7 6 ICCIH - 74OL6001-6011 ICCIL - 74OL6000-6010 VCCI = 5.5V ICCIH - 74OL6000-6010 ICCIL - 74OL6001-6011 0 II - INPUT CURRENT (A) IIH -100 VCCI = 5.5V VIH = 4.5V VIL = 0.4V IIL -200 -300 -40 -20 0 20 40 60 80 100 5 -40 -20 0 20 40 60 80 100 TA - AMBIENT TEMPERATURE (C) TA - AMBIENT TEMPERATURE (C) Figure 3. Output Supply Current vs. Ambient Temperature 15 IO - OUTPUT SUPPLY CURRENT (mA) Figure 4. Output Current vs. Ambient Temperature 60 50 40 30 20 10 0 -10 -20 IOH (74OL6000/6001) VCCI = 4.5V VCCO = 4.5V VOL = 0.6V VOH = 2.4V IOL ICCO - OUTPUT SUPPLY CURRENT (mA) 12 9 6 74OL6010/6011 VCCI = 5.5V VCCO = 15V 74OL6010/6011 VCCI = 5.5V VCCO = 5.5V ICCOH ICCOL ICCOH ICCOL ICCOH ICCOL 3 74OL6000/6001 VCCI = 5.5V VCCO = 5.5V 0 -40 -20 0 20 40 60 80 100 -30 -40 -20 0 20 40 60 80 100 TA - AMBIENT TEMPERATURE (C) TA - AMBIENT TEMPERATURE (C) Figure 5. High-Level Output Voltage vs. Ambient Temperature 5 VOH - HIGH-LEVEL OUTPUT VOLTAGE (V) VCCI = 4.5V VCCO = 4.5V IOH = -400A Figure 6. Low-Level Output Voltage vs. Ambient Temperature 0.5 VOL - LOW-LEVEL OUTPUT VOLTAGE (V) 4 0.4 @ IOL = 16mA 0.3 3 2 @ IOL = 4mA 0.2 1 VCCI = 4.5V VCCO = 4.5V 0.1 -40 -20 0 20 40 60 80 100 0 -40 -20 0 20 40 60 80 100 TA - AMBIENT TEMPERATURE (C) TA - AMBIENT TEMPERATURE (C) (c) 2003 Fairchild Semiconductor Corporation Page 7 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER 74OL6000 74OL6001 74OL6010 74OL6011 LSTTL TO Figure 7. 74OL6010/11 Leakage Current vs. Ambient Temperature 5 Figure 8. 74OL6000/01 Switching Times vs. Ambient Temperature VCCI = 5.0V VCCO = 5.0V P.W = 200ns PERIOD = 1S tPLH tPHL tr IOH - LEAKAGE CURRENT (A) 4 VCCIN = 4.5V VCCO = 15V VOUT = 15V 200 SWITCHING TIME (ns) 100 50 3 2 10 5 tf 1 0 -40 -20 0 20 40 60 80 100 1 -40 -20 0 20 40 60 80 100 TA - AMBIENT TEMPERATURE (C) TA - AMBIENT TEMPERATURE (C) Figure 9. 74OL6010/11 Switching Times vs. Ambient Temperature VCCO = 5V VCCO = 15V VCCI = 5V 200 SWITCHING TIME (ns) 100 50 RL = 470 P.W = 200ns PERIOD = 1S tPLH tPLH tr tPHL tr Figure 10. Common Mode Rejection vs. Common Mode Voltage CM - COMMON MODE TRANSIENT IMMUNITY (KV/S) 11 10 9 8 7 6 5 4 3 2 1 0 500 1000 15000 2000 2500 VCCO = 5V VCCO = 5V VOH = 2V VOL = 0.8V RL = 470 (74OL6010/6011) 10 5 tf tf 1 -40 -20 0 20 40 60 80 100 TA - AMBIENT TEMPERATURE (C) VCM - COMMON MODE TRANSIENT Figure 11. Supply Current vs. Supply Voltage 12 ICC ICCO Figure 12. Power Dissipation vs. Ambient Temperature PT - TOTAL PACKAGE POWER DISSIPATION (mW) MAXIMUM ALLOWABLE POWER DISSIPATION @ TA = 25C 10 ICC - SUPPLY CURRENT (mA) 300 8 @TA = 55C 6 VCCO RANGE FOR 74OL6000/6001 4 200 VCCI = 5.5V @TA = 70C @TA = 85C 100 2 VCCI = 4.5V 0 0 4 5 6 7 8 9 10 11 12 13 14 15 VCCO - OUTPUT SUPPLY VOLTAGE (V) 4 5 6 7 8 9 10 11 12 13 14 15 VCC - SUPPLY VOLTAGE (V) (c) 2003 Fairchild Semiconductor Corporation Page 8 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER Figure 14. Input Current vs. Input Voltage 100 LSTTL TO 74OL6000 74OL6001 74OL6010 74OL6011 Figure 13. Input Threshold Voltage vs. Ambient Temperature 1.6 VINTH - INPUT THRESHOLD VOLTAGE (V) 1.5 IIN - INPUT CURRENT (A) 0 1.4 1.3 1.2 -100 1.1 1.0 0.0 -40 VCCI = 5.0V VCCO = 5.0V -200 VCCI = 4.5V -300 -20 0 20 40 60 80 100 0 1 2 3 4 5 6 TA - AMBIENT TEMPERATURE (C) VIN - INPUT VOLTAGE (V) Figure 15. Switching Time Test Circuit Figure 16. Common Mode Rejection Test Circuit VCCO +5 V VCCI +5 V .1F PULSE GEN PW =200ns PERIOD = 1S tr = 5ns Zo = 50 1 6 .1F VCCO +5 V 470 (74OL6010/11) H/L L/H .1F 1k 1 6 .1F 470 (74OL6010/11) 2 5 2 5 CL* VO 3 6 3 4 *CL = 15pF STRAY CAPACITANCE INCLUDING PROBE + VCM - (c) 2003 Fairchild Semiconductor Corporation Page 9 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER 74OL6000 74OL6001 74OL6010 74OL6011 LSTTL TO Figure 17. 74OL6000/01 Switching Times vs. Ambient Temperature Figure 18. Switching Parameters 74OL6010/11 INPUT, VI INPUT, VI 3.2V 1.3V tPLH tPHL 90% OUTPUT, VO (74OL6000) tr tf tf tr 90% OUTPUT, VO (74OL6001) tPHL tPLH 1.3V 10% 1.3V 10% 3.2V 1.3V tPLH tPHL 90% OUTPUT, VO (74OL6010) tr tf tf tr 50% 10% 90% OUTPUT, VO (74OL6011) tPHL tPLH 50% 10% Figure 19. Common Mode Rejection Waveforms 50V VCM 0V VOH dVCM dt = VCM tr Figure 20. Suggested PCB Lay-Out INPUT VCC BUS INPUT GND BUS OUTPUT GND BUS OUTPUT VCC BUS CMH 1 VO = 2.0V (MIN.) 6 5 4 .1F DATA OUT DATA IN VO = 0.8V (MAX.) .1F 2 3 VOL CML NOTE 1. The VCCO and VCCI supply voltages to the device must each be bypassed by a 0.1F capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristics. Its purpose is to stabilize the operation of the highgain amplifiers. Failure to provide the bypass will impair the DC and switching properties. The total lead length between capacitor and optocoupler should not exceed 1.5mm. See Fig. 20. 2. Device considered a two-terminal device. Pins 1, 2 and 3 shorted together, and Pins 4, 5 and 6 shorted together. 3. For example, assuming a VCCI of 5.0V, and an ambient temperature of 70C, the maximum allowable VCCO is 12.1V. (c) 2003 Fairchild Semiconductor Corporation Page 10 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER 74OL6000 74OL6001 74OL6010 74OL6011 LSTTL TO Package Dimensions (Through Hole) PIN 1 ID. Package Dimensions (Surface Mount) 0.350 (8.89) 0.330 (8.38) 3 2 1 0.270 (6.86) 0.240 (6.10) PIN 1 ID. 0.270 (6.86) 0.240 (6.10) SEATING PLANE 0.070 (1.78) 0.045 (1.14) SEATING PLANE 0.350 (8.89) 0.330 (8.38) 4 5 6 0.070 (1.78) 0.045 (1.14) 0.300 (7.62) TYP 0.200 (5.08) 0.115 (2.92) 0.200 (5.08) 0.165 (4.18) 0.020 (0.51) MIN 0.100 (2.54) TYP 0.016 (0.41) 0.008 (0.20) 0.154 (3.90) 0.100 (2.54) 0.020 (0.51) MIN 0.016 (0.40) 0.008 (0.20) 0.022 (0.56) 0.016 (0.41) 0.016 (0.40) MIN 0.315 (8.00) MIN 0.405 (10.30) MAX 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) TYP 0 to 15 0.300 (7.62) TYP Lead Coplanarity : 0.004 (0.10) MAX Package Dimensions (0.4" Lead Spacing) PIN 1 ID. Recommended Pad Layout for Surface Mount Leadform 0.270 (6.86) 0.240 (6.10) 0.070 (1.78) 0.060 (1.52) 0.350 (8.89) 0.330 (8.38) 0.070 (1.78) 0.045 (1.14) 0.415 (10.54) 0.100 (2.54) 0.295 (7.49) 0.030 (0.76) SEATING PLANE 0.200 (5.08) 0.135 (3.43) 0.154 (3.90) 0.100 (2.54) 0.004 (0.10) MIN 0.016 (0.40) 0.008 (0.20) 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) TYP 0 to 15 0.400 (10.16) TYP NOTE All dimensions are in inches (millimeters) (c) 2003 Fairchild Semiconductor Corporation Page 11 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER 74OL6000 74OL6001 74OL6010 74OL6011 LSTTL TO ORDERING INFORMATION Option S SD W 300 300W 3S 3SD Order Entry Identifier .S .SD .W .300 .300W .3S .3SD Description Surface Mount Lead Bend Surface Mount; Tape and Reel 0.4" Lead Spacing VDE 0884 VDE 0884, 0.4" Lead Spacing VDE 0884, Surface Mount VDE 0884, Surface Mount, Tape and Reel MARKING INFORMATION 1 74OL6000 V XX YY K 3 4 5 2 6 Definitions 1 2 3 4 5 6 Fairchild logo Device number VDE mark (Note: Only appears on parts ordered with VDE option - See order entry table) Two digit year code, e.g., `03' Two digit work week ranging from `01' to `53' Assembly package code (c) 2003 Fairchild Semiconductor Corporation Page 12 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER 74OL6000 74OL6001 74OL6010 74OL6011 LSTTL TO Reflow Profile (Black Package, No Suffix) 300 Temperature (C) 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 3 225 C peak 215C, 10-30 s Time above 183C, 60-150 sec Ramp up = 3C/sec 3.5 4 4.5 * Peak reflow temperature: 225C (package surface temperature) * Time of temperature higher than 183C for 60-150 seconds * One time soldering reflow is recommended Time (Minute) (c) 2003 Fairchild Semiconductor Corporation Page 13 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER 74OL6000 74OL6001 74OL6010 74OL6011 LSTTL TO APPLICATION Local area data communication systems can greately improve their noise immunity by including OPOTOLOGIC gates in the design. The Optologic input amplifier offers the feature of very high input impedance that permits their use as bridged line receivers. The system show above illustrates an optically isolated transmitter and multidrop receiver system. The network uses a 74OL6000 and buffer (Figure D) to isolate the transmitter and drive the 75 coax cable. This application uses a 1000 ft. aerial suspension 75 CATV coax cable with data taps at 250 ft. intervals. The 74OL6001s function as bridged receivers, and as many as 30 receivers could be placed along the line with minimal signal degradation. The communication cable is terminated with a single 75 load at the far end of the line. Signal quality "Eye Pattern" is shown in Figures A, B and C with a 10MBaud NRZ Psuedo-Random Sequence (PRS). Traces 1-3 in Figure A describes the transmitter section. Traces 4-7 in Figure B show the output of the four Optologic bridged terminations. Traces 8-11 in Figure C illustrate "Eye Pattern" as seen at the output of a 74LS04 logic gate. The data quality is well preserved in that only a 30% Eye closure is seen at the receiver located 1000 ft. from the transmitter. The data communication system is completely optically isolated from all of the terminal equipments. Power for the transmitter (VCCO) and receiver (VCCI) is taken from an isolated power supply and distributed through a drain or messenger wire. Figure A Figure B Figure C HORIZONTAL = 20 ns/DIV VERTICAL = 2 V/DIV 42-11 HORIZONTAL = 20 ns/DIV VERTICAL = 2 V/DIV 42-12, 02 HORIZONTAL = 20 ns/DIV VERTICAL = 2 V/DIV 42-13/03 0.1 F 1.1 K 10 PRSG 100 ns BIT INTERVAL 1 2 3 1000 FT. 75 TERMINAION 74 OL6000 BUFFER 250 FT. 250 FT. 250 FT. 250 FT. 100 F 2N4252 74 OL 6001 2N4252 1.1 K 74 OL 6001 74 OL 6001 74 OL 6001 4 8 2N2222 5 LS04 6 LS04 7 LS04 9 10 11 LS04 1 K ALL DIODES 1N6263 Figure D Buffer (c) 2003 Fairchild Semiconductor Corporation Page 14 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER 74OL6000 74OL6001 74OL6010 74OL6011 LSTTL TO DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. (c) 2003 Fairchild Semiconductor Corporation Page 15 of 15 10/1/03 This datasheet has been download from: www..com Datasheets for electronics components. |
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